View TS52003_7685515.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

- 1 - ts520 03 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc description features typical application the TS52003 is a dc/dc synchronous switching super capacitor charger with fully integrated power switches, internal compensation, and full faul t protection. the TS52003 utilizes a temperature - independent photovoltaic maximum power point tracking ( mpp t - lite? ) calculator to optimize power out put from the source during full - charge mode. the switching frequency of 1mhz enables the use of small filter components, which result in smaller board space and reduced bom costs. in full - charge mode the duty cycl e is controlled by the mpp t - lite? regulator. once termination voltage is reached, the regulator operates in voltage mode. when the regulator is disabled (en is low ), the device draws less than 15 ua quiescent current from v out . the TS52003 integrates a w ide range of protection circuitry; including input supply under - voltage lockout, output over - voltage protection, current limit, and thermal shutdown. the TS52003 includes supervisory reporting through the nflt (inverted fault) open drain output to interfa ce other components in the system. device programming is achieved by an i2c interface through scl and sda pins. h igh efficiency supercap charger for photovoltaic sources ? utilizes a temperature - independent pv mppt - lite? regulation scheme ? vout reverse current blocking ? wide input voltage range: 3.2v to 7.2v ? up to 1.5a continuous output current ? programmable temperature - compensated termination voltage with a 1% tole rance ? user programmable termination voltage ? high efficiency C up to 92% at typical load ? current mode pwm control in constant voltage ? input supply under voltage lockout ? full protection for v out over - voltage ? device over - current and over - temperature protectio n ? i2c program interface with eeprom registers ? v out reverse current blocking ? charge status indication summary specifications ? packaged in a 16pin qfn (4x4) applications ? off - grid systems ? wireless sensor networks ? smoke detectors ? hvac controls g n d e n s w n f l t v o u t s c l p g n d c o u t l o u t r s e n s e v i n s d a p h o t o v o l t a i c c e l l s v s e n s e s u p e r c a p r p u l l u p ( o p t i o n a l ) v d d r p u l l u p ( o p t i o n a l ) v d d c i n v d d c v d d t s 5 2 0 0 3
- 2 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 pinout figure 1b: package pinout diagram pin description pin symbol pin # function description sw 1 switching voltage node connected to 4.7uh (typical) inductor vin 2 photovoltaic input voltage input voltage v sense 3 current sense positive input positive input for the mpp current loop. v out 4 super cap voltage regulator feedback input gnd 5 gnd primary ground for the majority of the device except the low - side power fet. en 6 enable input above 2.2v the device is enabled. gnd the pin to disable the device. includes internal pull - up. nflt 7 inverted fault open - drain output. vdd 8 internal 3.3v supply output connected to 100nf capacitor to gnd 9 unused gnd in application 10 unused gnd in application vin 11 photovoltaic input voltage input voltage scl 12 clock input i2 c clock input. sda 13 data input/output i2 c data open - drain output. sw 14 switching voltage node connected to 4.7uh (typical) inductor pgnd 15 power gnd gnd supply for internal low - side fet/integrated diode pgnd 16 power gnd gnd supply for internal low - side fet/integrated diode t s 5 2 0 0 3 q f n 1 6 4 x 4 t o p / s y m b o l i z a t i o n v i e w v i n v s e n s e v o u t s w v i n n c n c s c l s w p g n d p g n d s d a n f l t e n g n d v d d
- 3 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 functional block dia gram figure 2 : TS52003 block diagram v i n v o u t c u r r e n t c o n t r o l g a t e d r i v e g a t e d r i v e g a t e d r i v e c o n t r o l v o u t s w o s c i l l a t o r r a m p g e n e r a t o r c o m p a r a t o r e r r o r a m p g n d m o n i t o r & c o n t r o l o v e r v o l t a g e p r o t e c t i o n v o u t v i n v i n ? e n p g n d n f l t c o u t l o u t s u p e r c a p c o m p e n s a t i o n n e t w o r k b a c k g a t e b l o c k i n g p h o t o v o l t a i c c e l l s ~ 5 v @ 4 5 0 m a v r e f v o u t r s e n s e v s e n s e m p p & c u r r e n t c o n t r o l i 2 c i n t e r f a c e s c l s d a v i n c i n v d d c v d d v d d r e g u l a t o r v i n
- 4 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 absolute maximum rat ings over operating free C air temperature range unless otherwise noted (1,2 ,3 ) parameter range unit vin, en , nflt , scl, sda , v out , vsense - 0.3 to 8 v sw - 1 to 8.8 v vdd - 0.3 to 3. 6 v operating junction temperature range, t j - 40 to 125 ? c storage temperature range, t stg - 65 to 150 ? c electrostatic discharge C human body model 2k v electrostatic discharge C machine model +/ - 200 v lead temperature (soldering, 10 seconds) 260 ? c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rati ngs only and functional operation of the device at these or any other conditions beyond those indicated under recommended ope rating conditions is not implied. exposure to absolute C maximum C rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) esd testing is performed according to the respe ctive jesd22 jedec standard. thermal characterist ics symbol parameter value unit ? ja thermal resistance junction to air (note 1) 50 c/w note 1: assumes 4x4 qfn - 16 in 1 in 2 area of 2 oz copper and 25 ? c ambient temperature. recommended operatin g con ditions symbol parameter min typ max unit vin photovoltaic input operating voltage 3.2 5.3 7.2 v r sense sense resistor 50 m ? l out output filter inductor typical value (note 1) 4.7 uh c out output filter capacitor typical value (note 2) 4.7 uf c ou t - esr output filter capacitor esr 100 m ? c in input supply bypass capacitor typical value (note 3) 3.3 10 uf c vdd vdd supply bypass capacitor value (note 2) 70 100 130 nf t a operating free air temperature - 40 85 ? c t j operating junction temperature - 40 125 ? c note 1: for best performance, an inductor with a saturation current rating higher than the maximum v out load requirement plus the inductor current ripple. note 2: for best performance, a low esr ceramic capacitor should be used. note 3: for best performance, a low esr ceramic capacitor should be used. if c in is not a low esr ceramic capacitor, a 0.1uf ceramic capacitor should be added in parallel to c in .
- 5 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 characteristics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless ot herwise noted) symbol parameter condition min typ max unit vin supply voltage vin photovoltaic voltage input 3.2 5.3 7.2 v i cc - norm quiescent current normal mode i load = 0a 3 ma i cc - d isable quiescent current disable mode en = 0v 15 50 ua vout leakag e i out - leak leakage current en = 0v, vout = 2.7v 10 ua i out - back reverse current v out > vin, vout = 2.7v 10 ua vin under - voltage lockout vin - uv input supply under - voltage threshold vin increasing 3. 1 5 v vin - uv_hyst input suppl y under - voltage threshold hysteresis 100 200 mv osc f osc oscillator frequency 0.9 1 1.1 mhz nflt open drain output t nflt nflt release timer 0 ms i oh - nflt high - level output leakage v nflt = 5.3v 0.1 ua v ol - nflt low - level output voltage i nflt = - 1ma 0.4 v en/scl/sda input voltage thresholds v ih high level input voltage 2.2 v v il low level input voltage 0.8 v v hyst input hysteresis 200 mv i in - en input leakage v en =vin 0.1 ua v en =0v - 2.0 ua i in - scl input leakage v scl =vin 55 ua v scl =0 v - 0.1 ua i in - sda input leakage v sda =vin 0.1 ua v sda =0v - 0.1 ua v ol - sda low - level output voltage i sda = - 1ma 0.4 v thermal shutdown tsd thermal shutdown junction temperature 150 170 c tsd hyst tsd hysteresis 10 c
- 6 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 charger char acteristics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter condition min typ max unit charging regulator: l=4.7uh and c=4.7uf i out - fc output current limit in full - charge mode i out = 1 .5 a i out - 10 % i o ut i out + 10 % a v out termination voltage tolerance v out - 1% v out v out + 1% v t fc full - charge timer 20 0 1400 m in r dson high side switch on resistance i sw = - 1a, t j =25c 250 m? sw = 1a, t j =25c 150 m? out max ou tput current 1.5 a i ocd over - current detect hs switch current 2.5 a v out - ov v out over - voltage threshold 101% v out 102% v out 103% v out v out - ov_hyst v out over - voltage hysteresis 0.2 % v out 0.4 % v out 0.6 % v out duty max max duty cycle 9 8 % i 2 c interface timing req uirements electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter standard mode fast mode (1) unit min max min max f scl i 2 c clock frequency 0 100 0 400 khz t sch i 2 c clock high time 4 0. 6 s t scl i 2 c clock low time 4.7 1.3 s t sp (2) i 2 c tolerable spike time 0 50 0 50 ns t sds i 2 c serial data setup time 250 25 0 ns t sdh i 2 c serial data hold time 0 0 s t icr (2) i 2 c input rise time 1000 300 ns t icf (2) i 2 c input fall time 300 3 00 ns t ocf (2) i 2 c output fall time; 10 pf to 400 pf bus 300 300 n s t buf i 2 c bus free time between stop and start 4.7 1.3 s t sts i 2 c start or repeated start condition setup time 4.7 0.6 s t sth i 2 c start or repeated start condition hold time 4 0 .6 s t sps (2) i 2 c stop condition setup time 4 0.6 s (1) the i2c interface will operate in either standard or fast mode. (2) parameters not tested in production.
- 7 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 functional description the TS52003 is a fully - integrated super capacitor charger ic b ased on a highly - efficient switching topology. it includes a maximum power point t racking (mpp t ) function to optimize its input voltage to extract the maximum possible power from a photovoltaic cell. it includes configur ability for termination voltage and charge current. a 1 mhz internal switching frequency facilitates low - cost lc filter combinations. when enabled, the TS52003 will provide the maximum power available from a photovoltaic cell until the output voltage reaches the termination point. at that point, it will begin to regulate voltage. it will do so until a fault is detected, it is disabled or the output voltage drops below the termination point. internal protection details internal current limit the current through the inductor is sense d on a cycle by cycle basis and if current limit is reached, it will abbreviate the cycle. current limit is always active when the regulator is enabled. thermal shutdown if the temperature of the die exceeds 170c (typical), the sw outputs will tri - stat e to protec t the device from damage. the nflt and all other protection circuitry will stay active to inform the system of the failure mode. once the device cools to 160c (typical), the device will attempt to start up again. if the device reaches 170c, the shutdown/restart sequence will repeat. vin under - voltage lockout the device is held in the off state until vin reaches 3. 15 v. there is a 20 0mv hysteresis on this input, which re quires the input to fall below 2 . 95v before the device will disable. vout over - voltage protection the TS52003 has an output protection circuit designed to shutdown the charging profile if the output voltage is greater than the termination voltage. the termination voltage can change based on user programming, so the pr otection threshold is set to 2% above the termination voltage. shutting down the charging profile puts the TS52003 in a fault condition.
- 8 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 serial interface the TS52003 features an i 2 c slave interface which offers advanced control and diagnostic features . i 2 c operation offers configuration control for termination voltages, charge currents, and charge timeouts. i 2 c operation also offers fault and warning indicators. whenever a fault is detected, the associated status bit in the status register is set an d the nflt pin is pulled low. whenever a warning is detected, the associated status bit in the status register is set, but the nflt pin is not pulled low. reading of the status register resets the fault and warning status bits, and the nflt pin is releas ed after all fault status bits have been reset. i 2 c subaddress definition figure 3 : sub - address in i 2 c transmission i 2 c bus operation the TS52003 has a slave i 2 c interface that supports standard and fast mode data rates, auto - sequencing, and is com pliant to i 2 c standard version 3.0. i 2 c is a two - wire serial interface where the two lines are serial clock (scl) and serial data (sda). sda must be connected to a positive supply through an external pull - up resistor. the devices communicating on this bus can drive the sda line low or release it to high impedance. the device that initiates the i 2 c transaction becomes the master of the bus. communication is initiated by the master sending a start condition, a high - to - low transition on sda, while the s cl line is high. after the start condition, the device address byte is sent, most significant bit (msb) first, including the data direction bit (r/nw). after receiving the valid address byte, the device responds with an acknowledge (ack). an ack is a lo w on sda during the high of the ack related clock pulse. on the i 2 c bus, during each clock pulse only one data bit is transferred. the data on the sda line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as start or stop control commands. a low - to - high transition on sda while the scl input is high indicates a stop condition and is sent by the master (see figure 4 ). any number of data bytes can be transferred from the transmitter to r eceiver between the start and the stop conditions. each byte of eight bits is followed by one ack bit. the sda line must be released by the transmitter before the receiver can send an ack bit. the receiver that acknowledges must pull down the sda line du ring the ack clock pulse, so that the sda line is stable low during the high pulse of the ack - related clock period. when a slave receiver is addressed, it must generate an ack after each byte is received. similarly, the master must generate an ack after e ach byte that it receives from the slave transmitter. to ensure proper operation, setup and hold times must be met. an end of data is signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has been c locked out of the slave. this is done by the master receiver by holding the sda line high. the transmitter must then release the data line to enable the master to generate a st op condition.
- 9 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 figure 4 : i 2 c start / stop protocol figure 5 : i 2 c data transmission timing
- 10 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 register description (device address = 0x48) register address (hex) name default description 0 00 status 0x00 status bit register 1 n/a n/a n/a register not implemented 2 02 config1 (1) eeprom configuration register 3 n /a n/a n/a register not implemented 4 04 config3 (1) eeprom configuration register 5 - 16 n/a n/a n/a registers not implemented 17 11 config_enable 0x00 enable configuration register access 18 12 eeprom_ctrl (1) 0x00 eeprom control register status regis ter (status) address C 0x00h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name vout_ov not used not used not used tsd not used vin_uv not used read/write r r r r r r r r field name bit definition (2 ) vout _ov vout over - voltage tsd thermal shutdown vin_uv vi n under - voltage (1) config and eeprom_ctrl registers are only accessible when config_enable register is written. (2) fault is defined as vout_ov . warnings are de fined as tsd, and vin_uv. faults cause the nflt pin to be pulled low, warnings do not cause the nflt pin to be pulled low. all status bits are cleared after register read access. nflt pin will go high impedance (open drain output) after the status register has been read and all status bits have been reset.
- 11 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 configuration regist er (config1) address C 0x02h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name not used v_term [2:0] not used read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition v_term [2:0] voltage termination configuration 000 C C C C C C C C configuration regist er (config3) address C 0x04h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name max_chrg_curr [3:0] not used read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition max_chrg_curr [3:0] maximum charge current configuration 0000 C C C C C C C C C C C C C C C C
- 12 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 enable configuration register (config_ena ble) address C 0x11h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name not used not used not used not used not used not used not used en_cfg read/ write r r r r r r r r/w reset value 0 0 0 0 0 0 0 0 field name bit definition en_cfg enable access control bit for configuration registers 2 and 4 0 C C eeprom control regis ter (eeprom_ctrl) address C 0x12h data bit d 7 d6 d5 d4 d3 d2 d1 d0 field name not used not used not used not used not used not used not used ee_prog read/write r r r r r r r r/w reset value 0 0 0 0 0 0 0 0 field name bit definition ee_prog (1) eeprom program control bit for configuration regist ers 2 and 4 0 C C ee_prog note: inputs vin and en must be present for 200 ms. external component s election the internal compensation is optimized for a 4.7uf output capacitor and a 4.7uh inductor. to keep the output ripple low, a low esr (less than 35mohm) ceramic is recommended.
- 13 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 package mechanical d rawings
- 14 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 application using a multi - layer pcb to maximize the efficiency of this packag e for application on a single layer or multi - layer pcb, certain guidelines must be followed when laying out this part on the pcb. the following are guidelines for mounting the exposed pad ic on a multi - layer pcb with ground a plane . jedec standard fr4 pcb cross - section: multi - layer board (cross - sectional view) in a multi - layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. the efficiency of this method depends on several factors, including die area, number of thermal vias, thickness of copper, etc. package thermal pad solder pad (land pattern) thermal via's package outline package and pcb land configuration for a multi-layer pcb ( square ) package solder pad package solder pad ( bottom trace ) thermal via component traces thermal isolation power plane only 1 . 5748 mm 0 . 0 - 0 . 071 mm board base & bottom pad 0 . 5246 - 0 . 5606 mm power plane ( 1 oz cu ) 1 . 0142 - 1 . 0502 mm ground plane ( 1 oz cu ) 1 . 5038 - 1 . 5748 mm component trace ( 2 oz cu ) 2 plane 4 plane
- 15 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 the above drawing is a representation of how the heat can be conducted away from the die using an exposed pad package. each application will have different requirements and limitations and therefore the user should use sufficient copper to dissipate the power in the system. the output current rating for the linear regulators may have to be de - rated for ambient temperatures above 85c. the de - rate v alue will depend on calculated worst case power dissipation and the thermal management implementation in the application. application using a single layer pcb layout recommendations for a single layer pcb: utilize as much copper area for power managem ent. in a single layer board application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method (solder paste or thermal conductive epoxy). in both of the methods mentioned above it is advisable to use as much copper traces as possible to dissipate the heat. important: if the attachment method is not implemented correctly, the functionality of the product is not guaranteed. power dissipation capability will be adversely affected if the device is in correctly mounted onto the circuit board. mold compound die epoxy die attach exposed pad solder thermal vias with cu plating single layer , 2 oz cu ground layer , 1 oz cu signal layer , 1 oz cu bottom layer , 2 oz cu 20 % cu coverage 90 % cu coverage 5 % - 10 % cu coverage note : not to scale use as much copper area as possible for heat spread package thermal pad package outline
- 16 - specifications subject to change www.triunesystems .com copyright ? 2011 , triune systems, llc TS52003 version 1. 2 legal notices information contained in this publication regarding device applications and the like is provided only for your convenience an d may be superseded by updates. it is your responsibility to ensure th at your application meets with your specifications. typical parameters which may be provided in triune systems data sheets and/or specifications can and do vary in different applications and actual performance may vary over time . all operating paramete rs, including typicals must be validated for your application by your technical experts. triune systems makes no represent ations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, i ncluding but not limited to its condition, quality, performance, merchantability or fitness for purpose. triune systems disclaims all liability arising from this information and its use. triune system products are not des igned, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustai n life, or for any other application in which the failure of the triune systems product could create a situation where personal inj ury or death may occur. should the buyer purchase or use triune systems products for any such unintended or unauthorized application, the buyer shall indemnify and hold triune systems, and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unautho rized use, even if such claim alleges that triu ne systems was negligent regarding the design or manufacture of the part. no licenses are conveyed, implicitly or otherwise, under any triune systems intellectual property rights. trademarks the triune systems? name and logo, mppt - lite?, and nanosmart? are trademarks of triune systems, llc. in the u.s.a.. all other trademarks mentioned herein are property of their respective companies. ? 2012 triune systems, llc. all rights reserved.

▲Up To Search▲

Price & Availability of TS52003

	To Download TS52003 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .